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october 2013 ? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1. 0.0 fan4840 haptic driver f or linear resonant actuator s (lras) FAH4840 haptic driver for linear resonant actuator s (lras) features ? direct drive of lra (linear resonant actuator) ? external pwm input (10 kh z to 250 kh z) with d ivider ? internal m otor e nable / d isable i nput ? auto r esonant t racking ? ldo p rovides s table h aptic e ffect with b attery d epletion ? low s hutdown c urrent : < 5 na ? fast w ake - u p t ime ? nearly r ail - to - r ail o utput s wing ? thermal s hutdown, over - c urrent s hutdown ? register - b ased c ontrol by i 2 c ? immersion touchsense ? 3000 certified ? package: 8 - lead micropak ? mlp all trademarks are the property of their respective owners. description the FAH4840 is a high - performance amplifier for mobile phones and other hand - held devices. the haptic driver takes a single - ended pwm input signal to control a linear resonant actuator (lra). the device utilizes an external 10 k hz to 250 k hz pwm signal capable of meeting the wide range of resonant frequencies needed for an lra haptics application s . the FAH4840 r egister map is accessible through an i 2 c serial communication port. applications ? mobile phones ? handheld devices ? any k ey pad interface ordering information part number top mark operating temperature range package packing method quantity FAH4840l8x yb - 40c to +85c micropak? mlp reel 5000 free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 2 FAH4840 haptic driver for linear resonant actuator s (lras) block diagram figure 1. block diagram pin configuration figure 2. pin assignments ( micropak mlp ) pin definitions name pin # type description sda 1 input i 2 c data input vdd 2 power power md n 3 output negative motor driver output md p 4 output positive motor driver output gnd 5 power ground pwm 6 input pwm input scl 7 input i 2 c cl ock input hen 8 input haptic motor enable/disable ( high : enable, low : disable) m d p m d n c o n t r o l l o g i c a n d r e g i s t e r w i t h b a c k e m f d e t e c t i o n s e r i a l i 2 c i n t e r f a c e s c l s d a p w m h e n g n d v d d p r o g r a m m a b l e l d o p o r b a n d g a p r e f e r e n c e u v l o o t p o c p p w m d e t e c t i o n v c m v c m d i f f a m p d r i v e r c o m p i s e n * r o e n free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 3 FAH4840 haptic driver for linear resonant actuator s (lras) absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd dc supply voltage - 0.3 6 . 0 v v io analog and digital i/o ( a ll i nput and o utput p ins) - 0.3 v cc +0.3 v reliability information symbol parameter min. typ. max. unit t j junction temperature + 150 c t stg storage temperature range - 65 + 150 c electrostatic discharge information symbol parameter max. unit esd human body model, ansi/esda/jedec js - 001 - 2012 4 k v charged device model, jesd22 - c101 1 latch - up test c ondition for l atch - u p c urrent 150 ma recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or desi gning to absolute maximum ratings. symbol parameter min. typ. max. unit t a operating temperature range - 40 +8 5 c v dd supply voltage range 2. 5 3. 3 4 .3 v z load load impedance 15 25 50 ? dissipation ratings this thermal data is measured with a high - k board (four - layer board, according to the jesd51 - 7 jedec standard.) package ? ja unit 8 - lead micropak mlp 280 c/w free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 4 FAH4840 haptic driver for linear resonant actuator s (lras) dc electrical characteristics t a = 25c, v dd = 3.3 v, v reg =2 .0 v , unless otherwise noted. symbol parameter conditions min. typ. max. unit f ipwm pwm input frequency square w ave i nput 10 250 k hz iih pwm input current pwm = 1.8 v 1 3 a iih hen input current hen = 1.8 v 1 3 a iil pwm input current pwm = 0 v 1 3 a iil hen input current hen = 0 v 1 3 a v ih input logic high (hen, pwm) 1.15 v v il input logic low (hen, pwm) 0.5 v c in input capacitance pwm capacitance to gnd or 1.8 v 6 10 pf v ol output voltage v dd =3.3 v, r l =15 , v ol =v ol(measure) - (v cm - v reg /2) , see waveforms below 0.02 mv v oh output voltage v dd =3.3 v, r l =15 , v oh =v oh(measure) - (v cm - v reg /2) , see w aveforms b elow 1.95 v i out output drive current v dd =3.3 v, v reg =3.0 v, r l = 15 ? 200 ma i outscp short - c ircuit p rotection v dd =3.3 v, v reg =3.0 v, mdp and mdn s horted t ogether and e ach s horted to g round 350 400 ma i dd1 supply current pwm=22.4 k h z 50% d uty, hen = high , r l = n o l oad 2 5 ma i dd2 supply current pwm=22.4 k h z 90/10% d uty, hen = high , r l = 25 77 ma i dd3 supply current pwm,hen = 0 v, r l = 25 15 a i dd4 supply current pwm, hen=0 v, v dd =2.5 v, a ddress 0 b it 7 s et to z ero 2.0 na v reg output v oltage r ange measure v reg , v dd per t able 1.4 2.0 3.2 v v rega output v oltage a ccuracy measure v reg - 2.5 2.5 % mdp mdn figure 3. output waveforms free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 5 FAH4840 haptic driver for linear resonant actuator s (lras) ac electrical characteristics t a = 25c, v dd = 3.3 v, v reg =2.0 v , unless otherwise noted. symbol parameter conditions min. typ. max. unit t wu wake - up time pwm=80/20% duty cycle, hen/pwm low to high , measure ment point pwm = 50%, output point = 90% 1 150 s t sd shutdown time pwm=80/20% duty cycle, hen high to low , measure ment point hen = 50%, output point = 90% 0.2 150 .0 s restrk auto resonance tracking pwm=22.4 khz 80/20% duty, r l = 25 ? - 2.5 2.5 hz t wu t sd figure 4. haptic enable / disable functional timing table 1. v dd vs . v reg supply v alues v reg_out (programmed voltage) v dd (v) 2.5 2.7 3.0 3.3 1.4 1.4 1.4 1.4 1.6 1.6 1.6 1.6 1.8 1.8 1.8 1.8 2.0 2.0 2.0 2.0 2.2 2.2 2.2 2.2 2.4 2.4 2.4 2.4 2.6 2.6 2.6 2.8 2.8 3.0 3.2 free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 6 FAH4840 haptic driver for linear resonant actuator s (lras) i 2 c dc electrical characteristics t a = 25c, v dd = 3.3 v, v reg =2 .0 v , unless otherwise noted. symbol parameter f ast m ode (400 k hz) min. max . unit v il low - level input voltage - 0.3 0. 6 v v ih high - level input voltage 1.3 v v ol low - level output voltage at 3 ma sink current (open - drain or open - collector) 0 0.4 v i ih high - level input current of each i/o pin, input voltage=v svdd - 1 1 a i il low - level input current of each i/o pin, input voltage=0 v - 1 1 a i 2 c ac electrical characteristics t a = 25c, v dd = 3.3 v, v reg =2.0 v, unless otherwise noted. symbol parameter fast mode (400 k hz) min. max. unit f scl scl clock frequency 0 400 k hz t hd;sta hold time (repeated) start condition 0.6 s t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t su;sta set - up time for repeated start condition 0.6 s t hd;dat data hold time 0 0.9 s t su;dat data set - up time ( 1 ) 100 ns t r rise time of sda and scl signals ( 2 ) 20+0.1c b 300 n s t f fall time of sda and scl signals ( 2 ) 20+0.1c b 300 n s t su;sto set - up time for stop condition 0.6 s t buf bus - free time between stop and start conditions 1.3 s t sp pulse width of spikes that must be suppressed by the input filter 0 50 n s notes: 1. a f ast - m ode i 2 c b us ? device can be used in a s tandard - m ode i 2 c bus system, but the requirement t su;dat ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the serial data (sda) line t r_max + t su;dat = 1000 + 250 = 1250 ns (according to the s tandard - m ode i 2 c b us specification) before the scl line is released. 2. c b equals the total capacitance of one bus line in pf. if mixed with h igh - s peed m ode devices, faster fall times are allowed according to the i 2 c specification. figure 5. definition of timing for full - speed m ode d evices on the i 2 c b us free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 7 FAH4840 haptic driver for linear resonant actuator s (lras) functional description i 2 c control writing to and reading from registers is accomplished via the i 2 c interface. the i 2 c proto col requires that one device on the bus initiates and controls all read and write operations. this device is called the master device. the master device generates the scl signal, which is the clock signal for all other devices on the bus. all other devic es on the bus are called slave devices. the FAH4840 is a slave device. both the master and slave devices can send and receive data on the bus. during i 2 c operations, one data bit is transmitted per clock cycle. all i 2 c operations follow a repeating nine - clock - cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ack) or not acknowledge (nack) from the receiving device. t here are no unused clock cycles during any operation; therefore, there must be no breaks i n the stream of data and acks/nacks during data transfers. for most operations, i 2 c protocol requires the sda line to remain stable (unmoving) whenever scl is high; i.e. transitions on the sda line can only occur when scl is low. the exceptions to this rul e are when the master device issues a start or stop condition. the slave device cannot issue a start or stop condition. start condition: this condition occurs when the sda line transitions from high to low while scl is high. the master device uses this condition to indicate that a data transfer is about to begin. stop condition: this condition occurs when the sda line transitions from low to high while scl is high. the master device uses this condition to signal the end of a data transfer. acknowledge and not acknowledge: when data is transferred to the slave device, the slave device sends acknowledge (ack) after receiving every byte of dat a. the receiving device sends an ack by pulling sda low for one clock cycle. when the master device is reading data from the slave device, the master sends an ack after receiving every byte of data. following the last byte, a master device sends a not ack nowledge (nack) instead of an ack, followed by a stop condition. a nack is indicated by leaving sda high during the clock after the last byte. slave address each slave device on the bus must have a unique address so the master can identify the device send ing or receiving data. the FAH4840 s lave address is 0000110x binary or 06 hex where x is the read/write bit. master write operations are indicated when x=0. master read operations are indicated when x=1. writing to and reading from the FAH4840 all read a nd write operations must begin with a start condition generated by the master. after the start condition , the master must immediately send a slave address (7 bits), followed by a read/write bit. if the slave address matches the address of the FAH4840 , the FAH4840 sends an ack after receiving the read/write bit by pulling the sda line low for one clock cycle. setting the pointer for all operations, the pointer stored in the command register must be pointing to the register that is going to be written or read. to change the pointer value in the command register, the read/write bit following the address must be 0. this indicates that the master writes new information into the command register. after the FAH4840 sends an ack in response to receiving the addr ess and read/write bit, the master must transmit an appropriate 8 - bit pointer value, as explained in the i 2 c registers section. the FAH4840 sends an ack after receiving the new pointer data. the pointer set operation is illustrated in figure 8 and figure 9 . any time a pointer set is performed, it must be immediately followed by a read or write operation. the command register retains the current pointer value between operations; therefore, once a register is indicated, subsequent read operations do not require a pointer set cycle. write operations always require the pointer be reset. reading if the pointer is already pointing to the desired register, the master can read from that register by sett ing the read/write bit (following the slave address) to 1. after sending an ack, the FAH4840 begins transmitting data during the following clock cycle. the master should respond with a nack, followed by a stop condition (see figure 6 ) . the master can read multiple bytes by responding to the data with an ack instead of a nack and continuing to send scl pulses, as shown in figure 7 , then the FAH4840 increments the pointer by one and sends the data from the next register. the master indicates the last data byte by responding with a nack, followed by a stop condit ion . to read from a register other than the one currently indicated by the command register, a pointer to the desired register must be set. immediately following the pointer set, the master must perform a repeat ed start condition (see figure 9 ) , which indicates to the FAH4840 that a new operation is about to occur. if the repeat ed start condition does not occur, the FAH4840 assumes that a write i s taking place and the selected register is overwritten by the upcoming data on the data bus. after the start condition, the master must again send the device address and read/write bit. this time, the read/write bit must be set to 1 to indicate a read. th e rest of the read cycle is the same as described in the previous paragraphs for reading from a preset pointer location. free datasheet http:///
? 2007 f airchild semiconductor corporation www.fairchildsemi.com writing all writes must be preceded by a pointer set, even if the pointer is already pointing to the desired register. immediately following the pointer set, the master must begin transmitting the data to be written. after transmitting each byte of data, the master must release the serial data (sda) line for one clock cycle to allow the FAH4840 to acknowledge receiving the byte. the write operation should be terminated by a stop condition from the master (see figure 8 ) . as with reading, the master can write m ultiple bytes by continuing to send data. the FAH4840 increments the pointer by one and accepts data for the next register. the master indicates the last data byte by issuing a stop condition. read / write diagrams figure 6. i 2 c read figure 7. i 2 c multiple byte read figure 8. i 2 c write figure 9. i 2 c write followed by read s d a s c l d 3 d 7 d 6 d 5 d 4 d 2 d 1 d 0 a 3 a 7 a 6 a 5 a 4 a 2 a 1 a c k n a c k r / w s l a v e a d d r e s s ( f r o m m a s t e r ) d a t a ( f r o m s l a v e ) a c k ( f r o m s l a v e ) n a c k ( f r o m m a s t e r ) s t a r t ( f r o m m a s t e r ) s t o p ( f r o m m a s t e r ) s d a s c l d 3 d 7 d 6 d 5 d 4 d 2 d 1 d 0 a 3 a 7 a 6 a 5 a 4 a 2 a 1 a c k r / w s l a v e a d d r e s s ( f r o m m a s t e r ) d a t a ( f r o m s l a v e ) a c k ( f r o m s l a v e ) a c k ( f r o m m a s t e r ) d 3 d 7 d 6 d 5 d 4 d 2 d 1 d 0 a c k n a c k d a t a ( f r o m s l a v e ) n a c k ( f r o m m a s t e r ) s t o p ( f r o m m a s t e r ) s t a r t ( f r o m m a s t e r ) p 3 p 7 p 6 p 5 p 4 p 2 p 1 p 0 a 3 a 7 a 6 a 5 a 4 a 2 a 1 r / w a c k s d a s c l a c k a c k ( f r o m s l a v e ) s l a v e a d d r e s s ( f r o m m a s t e r ) p o i n t e r ( f r o m m a s t e r ) d 3 d 7 d 6 d 5 d 4 d 2 d 1 d 0 a c k d a t a ( f r o m m a s t e r ) a c k ( f r o m s l a v e ) a c k ( f r o m s l a v e ) s t o p ( f r o m m a s t e r ) s t a r t ( f r o m m a s t e r ) p 3 p 7 p 6 p 5 p 4 p 2 p 1 p 0 a 3 a 7 a 6 a 5 a 4 a 2 a 1 r / w a c k s d a s c l a c k a c k ( f r o m s l a v e ) s l a v e a d d r e s s ( f r o m m a s t e r ) p o i n t e r ( f r o m m a s t e r ) a 7 a 6 a 5 a 4 s l a v e a d d r e s s ( f r o m m a s t e r ) a c k ( f r o m s l a v e ) r e p e a t s t a r t ( f r o m m a s t e r ) d 3 d 7 d 6 d 5 d 4 d 2 d 1 d 0 a 3 a 2 a 1 a c k n a c k r / w s l a v e a d d r e s s ( f r o m m a s t e r ) d a t a ( f r o m s l a v e ) a c k ( f r o m s l a v e ) n a c k ( f r o m m a s t e r ) s t a r t ( f r o m m a s t e r ) s t o p ( f r o m m a s t e r ) free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 9 FAH4840 haptic driver for linear resonant actuator s (lras) table 2. register map table adrs register type reset value bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h ctrl1 r/w 10000000 haptic_ en reserved reserved reserved en_lpf se vreg_ vcm 01h ctrl2 r/w 00110011 in_res[2:0] en_pw m_det vreg_out[3:0] 02h status1 r xxxx111x reserved reserved reserved reserved vdd_g vreg_ out_g vot reserved 03h ctrl_div1 r/w 01010011 pwm_div[7:0] 04h ctrl_div2 r/w 00000000 pwm_div[15:8] 05h ctrl_cali b1 r/w 00000011 resonance_margin[3:0] meas_delay [1:0] en_temp _reg calib_ en 06h ctrl_cali b2 r/w xxxx0011 reserved reserved reserved reserved pulse_num[2:0] sel_ avrg 07h ctrl_thr r/w 00000100 z_x_num[7:0] 08h calib_sta tus1 r x001000 reserved calib_ fail last_ level calib_ first calib_state[3:0] 09h calib_sta tus2 r 00000000 first_tag[7:0] 0ah calib_sta tus3 r 00000000 first_tag[15:8] 0bh calib_sta tus4 r 00000000 pwm_divisor_a[7:0] 0ch calib_sta tus5 r 00000000 pwm_divisor_a[15:8] 0dh calib_sta tus6 r 00000000 pwm_divisor_b[7:0] 0eh calib_sta tus7 r 00000000 pwm_divisor_b[15:8] 0fh calib_sta tus8 r 00000000 pwm_divisor[7:0] 10h calib_sta tus9 r 00000000 pwm_divisor[15:8] 11h calib_sta tus10 r 00000000 cnt_h[7:0] 12h calib_sta tus11 r 00000000 cnt_l[7:0] 13h calib_sta tus12 r 00000000 cnt_zx[7:0] 14h ctrl3 w/r xxxxxxx0 reserved reserved reserved reserved reserved reserved reserved sw_rst free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 10 FAH4840 haptic driver for linear resonant actuator s (lras) table 3. ctrl1 address : 0x00 reset value: 1xxxx 0 00 bit # name type function 7 haptic_en r/w 1: haptic d rive e nable m ode 0: power - d own m ode 6 :3 r eserved 2 en_lpf r/ w 1: enable internal 20 khz lpf 0: disable internal lpf 1 se r/w 1: single - ended m ode 0: differential m ode 0 vreg_vcm r/ w 1: outputs use v reg /2 as vcm o 0: outputs use v dd /2 as vcmo table 4. ctrl2 address : 0x01 reset value: 00110011 bit # name type function 7:5 in_res[2:0] r/w input resistance. 000: 8 k 001: 10 k 010: 12 k k k k k k 1: e nable pwm detection circuit 0: disable pwm detection circuit 3:0 vreg_out[3:0 ] r/w 0000 1.4 v 0001 1.6 v 0010 1.8 v 0011 2.0 v 0100 2.2 v 0101 2.4 v 0110 2.6 v 0111 2.8 v 1000 3.0 v 1001 3.2 v d uring lra calibration stage 1, v reg_out is always 2.0 v. free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 11 FAH4840 haptic driver for linear resonant actuator s (lras) table 5. status1 address: 0x02 reset value: xxxx111x bit # name type function 7:4 r eserved 3 vdd_g r 0: input voltage is not good (less uvlo), input voltage is less than 2.3 v (rising), 2.1 v (falling) 1: input voltage is good ( o ver uvlo) 2 vreg_out_ g r 0: regulator output is not good (v reg_out is less than 70% of vreg_out programmed) 1: regulator output is good ( 3 ) 1 vot r 0: over temperature protection is tripped 1: over temperature protection is not tripped 0 r eserved note: 3. hen must be high for vreg_out to be enabled . table 6. ctrl_div1 address : 0x03 reset value: 01010011 bit # name type function 7:0 pwm_div[7:0] r/w lsb of the pwm divisor. for example , if the intended resonance frequency is 175 hz and the pwm input clock frequency is 40 k hz , p rogram the pwm[15:0] register as: pwm_div[15:0] = (1/175)/(1/40 k hz) = 228(decimal) = e4(hex) pwm_div[15:8] = 00 pwm_div[7:0] = e4 counter range is from 01 to e4. d efault is 83 table 7. ctrl_div2 address : 0x04 reset va lue: 00000000 bit # name type function 7:0 pwm_div[15:8] r/w msb of the pwm divisor. default is 0 free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 12 FAH4840 haptic driver for linear resonant actuator s (lras) table 8. ctrl_calib1 address : 0x05 reset value: 00000011 bit # name type function 7:4 resonance _margin [3:0] r/w this is the % (of programmed pwm_div[15:0]) margin that is acceptable. the measured resonance frequency is compared against this margin. if within margins , the measured r esonance f requency is accepted, else it is discarded. 0000 no limit 0001 1/25 6 * 100 = %0.39 0010 1/128 * 100 = %0.78 0011 1/64 * 100 = %1.56 0100 1/32 * 100 = %3.12 0101 1/16 * 100 = %6.25 0110 1/8 * 100 = %12.5 0111 1/4 * 100 = %25.0 3:2 meas_dela y[1:0] r/w delay the zero crossing detection by a number of pwm clock cycles , which is calculated by below ratio multiple pwm_div. for example, if set to 00, the delay number is (pwm_div*1/8). 00: 1/8 01: 1/16 10: 1/32 11: 1/64 1 en_temp_ reg r/w if set to 1 , the detected pwm divisor value is stored in a t emp register and used at the starting of the next haptic event. if set to 0 , haptic cycles always use the initial set pwm_div. 0 calib_en r/w if set to 1 , the part perform s calibration, else no calibration. table 9. ctrl_calib2 address : 0x06 reset value: xxxx0011 bit # name type function 7:4 reserved 3:1 pulse_num [2:0] r/w determines the pulse number in stage 1 when calibration at beginning. the pulse number is #(pulse_num+1). 000: pulse number 1 001: pulse number 2 010: pulse number 3 011: pulse number 4 100: pulse number 5 101: pulse number 6 110: pulse number 7 111: pulse number 8 0 sel_avrg r/w 1: select average value of two periods as final lra period result. 0: select the detected first period as final lra period result. free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 13 FAH4840 haptic driver for linear resonant actuator s (lras) table 10. ctrl_thr address : 0x07 reset value: 00000100 bit # name type function 7 :0 z_x_num[ 7 :0] r/w threshold for transition region around zero - crossing point. it represents the jitter width around the zero - crossing point. when accumulative comparator result for one level ( high or low ) around the transition edge reaches the threshold, zero - crossing point is thought to be found. the threshold is programmed referring to pwm_div. to be safe, set the threshold a bit larger than the real transition region. table 11. calib_status1 address : 0x08 reset value: x0010000 bit # name type function 7 r eserved 6 calib_fail r after the measure ment delay period pass es , count perio d of 3*pwm_div. during this time, if the four zero - crossing points are not found, calibration fails. 5 last_level r indicate the last level ( high or low ) for detecting next zero - crossing point. 4 calib_first r indicate whether current resonant detection is the first after power on reset or not. 3:0 calib_state r resonant detection state machine. table 12. calib_status2 address : 0x09 reset value: 00000000 bit # name type function 7 :0 first_tag[7:0] r lsb bits of the tag for the first found zero - crossing edge. table 13. calib_status3 address : 0x0a reset value: 00000000 bit # name type function 7 :0 first_tag[15:8] r msb bits of the tag for the first found zero - crossing edge. table 14. calib_status4 address : 0x0b reset value: 00000000 bit # name type function 7 :0 pwm_divisor_a[7:0] r lsb bits of the resonant period calculated by the first zero - crossing point and third point. free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 14 FAH4840 haptic driver for linear resonant actuator s (lras) table 15. calib_status5 address : 0x0c reset value: 00000000 bit # name type function 7 :0 pwm_divisor_a[15:8] r msb bits of the resonant period calculated by the first zero - crossing point and third point. table 16. calib_status6 address : 0x0d reset value: 00000000 bit # name type function 7 :0 pwm_divisor_b[7:0] r lsb bits of the resonant period calculated by the second zero - crossing point and the fo u rth point. table 17. calib_status7 address : 0x0e reset value: 00000000 bit # name type function 7 :0 pwm_divisor_b[15:8] r msb bits of the resonant period calculated by the second zero - crossing point and the fo u rth point. table 18. calib_status8 address : 0x0f reset value: 00000000 bit # name type function 7 :0 pwm_divisor[7:0] r lsb bits of the final resonant period. pwm_divisor may comes from initial pwm_div, or pwm_divisor_a, or the average value of pwm_divisor_a and pwm_divisor_b. table 19. calib_status9 address : 0x10 reset value: 00000000 bit # name type function 7 :0 pwm_divisor[15:8] r msb bits of the final resonant period. table 20. cnt_h address: 0x11 reset value: 00000000 bit # name type function 7 :0 cnt_h[7:0] r high l evel c ounter during first edge detection. free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 15 FAH4840 haptic driver for linear resonant actuator s (lras) table 21. cnt_l address: 0x12 reset value: 00000000 bit # name type function 7 :0 cnt_l[7:0] r low l evel c ounter during first edge detection. table 22. cnt_h address : 0x13 reset value: 00000000 bit # name type function 7 :0 cnt_zx[7:0] r level c ounter used for zero - crossing points detection. table 23. ctrl3 address : 0x14 reset value: xxxxxxx0 bit # name type function 7 :1 r eserved 0 sw_rst w/r software reset bit, default is zero. when this bit is s et 1 , a negative pulse is generated and all the ongoing operation is stopped and all registers reset to default value s . this bit is self - clearing and changes back to high after the negative pulse. free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 16 FAH4840 haptic driver for linear resonant actuator s (lras) applications information figure 10. system block diagram figure 11. lra system block diagram m v d d g n d m d p m d n s d a s c l g p i o p w m h o s t f a h 4 8 4 0 s d a s c l p w m h e n p w m free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 17 FAH4840 haptic driver for linear resonant actuator s (lras) figure 12. lra system block diagram table 24. lra resonant actuator function pwm duty cycle ( 4 ) lra drive voltage at resonant frequency 90/10% pwm duty cycle 50/50% pwm duty cycle 10/90% pwm duty cycle note: 4. pwm frequency is a multiple of the lra resonant frequency. this is controlled by i 2 c register s ctrl _div1 and ctrl_div2 . for example , if the lra resonant frequency is 175 hz , t he pwm frequency would be 14.5 k hz and the i 2 c ctrl_div1 and ctrl_div2 regis ter s would be programmed to 1/83 . v d d g n d v d d g n d m d p m d n v d d g n d v d d g n d m d p m d n h o s t f a h 4 8 4 0 p w m s c l s d a m d n m d p a c t u a t o r g p i o e n g n d v d d v d d g n d v d d g n d m d p m d n free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 18 FAH4840 haptic driver for linear resonant actuator s (lras) internal ldo the internal ldo is designed for adjusta ble output voltage (v reg_out ), control led by a 16 - step i 2 c register. this provides flexibility, convenience, and configuration for low - power consumption. the ldo includes an internal circuit for short - circuit current pro tection. serial interface the i 2 c registers allow the user to program the motor type, pwm dividing ratio, power - down , and other functions . the device needs to function without any i 2 c input signals connected. thermal shutdown the device ha s thermal shutdown capability. if the junction temperature is above 1 5 0c , the temp erature control block shuts down and remains off until the tem perature goes below 134c. t he register value s are kept , so re - initialization is not required. over - c urrent l imitation the driver includes a current - limitation block to protect against an over - current condition. this is mainly a protection against a stuck spring condition. over - current shutdown is at 350 ma typic al ly . status registers the status re gister set monitors ldo input voltage, regulator output voltage , and over - temperature status. figure 13. typical performance characteristics 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 na vcc FAH4840 shut down current, software disable on, hen=0. pwm=0 free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 19 FAH4840 haptic driver for linear resonant actuator s (lras) physical dimensions figure 14. 8 - lead , micropa k mlp package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to v erify o r obtain the most recent revision. package specifications do not expand the terms of fairchilds worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/ma/mac08a.pdf . for current packing container specifications, visit fairchild semiconductors online packaging area: http://www.fairchildsemi.com/package/packagedetails.html?id=pn_mllf5 - 008 (0.09) (0.1) (0.2) 1.6 2x 0.05 0.00 1.6 2x c 0.05 c 4 3. drawing conforms to asme y.14m-1994 2. dimensions are in millimeters 1. package conforms to jedec mo-255 variation uaad bottom view 4. pin 1 flag, end of package offset mac08arev4 1 2 3 5 6 7 8 notes: 8x 0.25 0.35 3x 8x 1.0 4 0.5 8x 0.25 0.15 0.10 c a b 0.05 c 0.10 c top view index area b recommended landpattern a 0.10 c 0.55 max 0.05 c detail a 0.35 0.25 (0.15) (0.20) 0.35 0.25 detail a pin #1 terminal scale: 2x 5. drawing file name: mkt-mac08arev4 free datasheet http:///
? 2013 f airchild semiconductor corporation www.fairchildsemi.com FAH4840 ? rev. 1.0. 0 20 FAH4840 haptic driver for linear resonant actuator s (lras) free datasheet http:///
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